Design of a CMOS low-power and low-voltage four-quadrant analog multiplier-Reference-Cited by-同舟云学术

Design of a CMOS low-power and low-voltage four-quadrant analog multiplier

Published:2009-09-16 Issue:2 Volume:63 Page:307-312
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Liu Weihsing,Liu Shen-Iuan

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-009-9382-y.pdf

Reference29 articles.

1. Choi, J., Park, J., Kim, W., Lim, K., & Laskar, J. (2009). High multiplication factor capacitor multiplier for an on-chip PLL loop filter. Electronics Letters, 45(5), 239–240.

2. Boonchu, B., & Surakampontorn, W. (2006). CMOS voltage-mode analog multiplier: IEEE international symposium on circuits and systems (pp. 21–24), May, 2006.

3. Prommee, P., Somdunyakanok, M., Angkaew, K., Jodtang, A., & Dejhan, K. (2005). Single low-supply and low-distortion CMOS analog multiplier: IEEE international symposium on communications and information technology (Vol. 1, pp. 251–254), Oct, 2005.

4. Abbott, J., Plett, C., & Rogers, J. W. M. (2005). A 1.2 V CMOS multiplier for 10 Gbit/s equalization: Proceedings of the 31st European solid-state circuits conference (pp. 379–382), Sep, 2005.

5. Boonchu, B., & Surakampontorn, W. (2005). A new NMOS four-quadrant analog multiplier: IEEE international symposium on circuits and systems (Vol. 2, pp. 1004–1007), May, 2005.

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