A low-jitter clock multiplier using a simple low-power ECDLL with extra settled delays in VCDL
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-020-01597-x.pdf
Reference16 articles.
1. Kuo, C. H., Lai, H. J., & Lin, M. F. (2011). A multi-band fast-locking delay-locked loop with jitter-bounded feature. IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control,58(1), 51–59.
2. Sofimowloodi, S., Razaghian, F., & Gholami, M. (2019). Low-power high-frequency phase frequency detector for minimal blind-zone phase-locked loops. Circuits, Systems, and Signal Processing, 38, 498–511.
3. Estebsari, M., Gholami, M., & Ghahramanpour, M. J. (2017). A wide frequency range delay line for fast-locking and low power delay-locked-loops. Analog Integrated Circuits and Signal Processing,90(2), 427–434.
4. Guo, H., & Tadeusz, K. (2015). A DLL-based period synthesis. In 2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE). IEEE
5. Jee, D.-W. (2016). Fractional-N multiplying delay-locked loop with delay-locked loop-based injection clock generation. Electronics Letters,52(9), 694–695.
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