Leakage Power Reduction in Deep Submicron VLSI Circuits Using Delay-Based Power Gating
Author:
Publisher
Springer Science and Business Media LLC
Subject
Engineering (miscellaneous)
Link
http://link.springer.com/content/pdf/10.1007/s40009-019-00848-4.pdf
Reference8 articles.
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2. Henzler S (2007) Power gating. Power management of digital circuits in deep sub-micron CMOS technologies advanced microelectronics. Springer, Dordrecht, pp 69–167. https://doi.org/10.1007/1-4020-5081-x_5
3. Xu H, Vemuri R, Jone W-B (2011) Dynamic characteristics of power gating during mode transition. IEEE Trans Very Large Scale Integr Syst 19(2):237–249. https://doi.org/10.1109/tvlsi.2009.2033699
4. Mutoh S, Douseki T, Matsuya Y, Aoki T, Yamada J (1995) 1 V high-speed digital circuit technology with 0.5 μm multi-threshold CMOS. In: Sixth annual IEEE international ASIC conference and exhibit, pp 847–854. https://doi.org/10.1109/asic.1993.410836
5. Priya M, Baskaran K, Krishnaveni D (2012) Leakage power reduction techniques in deep submicron technologies for VLSI applications. Procedia Eng 30:1163–1170. https://doi.org/10.1016/j.proeng.2012.01.976
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