High resolution mutated dynamic precision power gated comparator for 9-bit SAR ADC

Abstract

Abstract Comparator design is a major challenge during the implementation of high resolution SAR ADCs. In this research, a mutated dynamic power gated comparator is designed to achieve the SAR ADC with ultra-low power and enhanced gain. The proposed power gated comparator is designed using 45nm CMOS technology, and it is tested at 3.3V and 5V. High speed and low power are achieved through transistor sizing and power gating techniques. Mismatch of transistors, the offset value is appropriately calculated using the input resistance of the differential amplifier and trans conductance. Also, the offset cancellation and digital calibration techniques are included in the design to enhance the precision, and to improve the performance of ADCs. For the proposed comparator, phase margin, gain, ICMR, power consumption, offset voltage, slew rate, load capacitance, propagation delay, kickback noise, and settling time are compared with the conventional comparator. The proposed design consumes only 4.2mW while operating at 5V and 1.5mW when the input voltage is 3.3V. The effective resolution of the SAR ADC is observed as 8.2 bit with the proposed power gated comparator.