Flip-flops soft error rate evaluation approach considering internal single-event transient
Author:
Publisher
Springer Science and Business Media LLC
Subject
General Computer Science
Link
http://link.springer.com/content/pdf/10.1007/s11432-014-5260-z.pdf
Reference19 articles.
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2. Gasiot G, Glorieux M, Clerc S, et al. Experimental soft error rate of several flip-flop designs representative of production chip in 32 nm CMOS technology. IEEE Trans Nucl Sci, 2013, 60: 4226–4231
3. Jagannathan S, Loveless T D, Bhuva B L, et al. Frequency dependence of alpha-particle induced soft error rates of flip-flops in 40-nm CMOS technology. IEEE Trans Nucl Sci, 2012, 59: 2796–2802
4. Mahatme N N, Gaspard N J, Jagannathan S, et al. Impact of supply voltage and frequency on the soft error rate of logic circuits. IEEE Trans Nucl Sci, 2013, 60: 4200–4206
5. Tang H, Cannon E. SEMM-2: a modeling system for single event upset analysis. IEEE Trans Nucl Sci, 2004, 51: 3342–3348
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