Design for reliability with the advanced integrated circuit (IC) technology: challenges and opportunities

Author:

Ji Zhigang,Chen Haibao,Li Xiuyan

Publisher

Springer Science and Business Media LLC

Subject

General Computer Science

Reference7 articles.

1. Auth C, Aliyarukunju A, Asoro M, et al. A 10nm high performance and low-power CMOS technology are featuring 3rd generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017

2. Huang R, Jiang X B, Guo S F, et al. Variability-and reliability-aware design for 16/14nm and beyond technology. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017

3. Ji Z, Zhang J F, Lin L, et al. A test-proven as-grown-generation (A-G) model for predicting NBTI under use-bias. In: Proceedings of Symposium on VLSI Technology (VLSI Technology), Kyoto, 2015

4. Yu Z Q, Zhang J Y, Wang R S, et al. New insights into the hot carrier degradation (HCD) in FinFET: new observations, unified compact model, and impacts on circuit reliability. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017

5. Ji Z, Hatta S F W M, Zhang J F, et al. Negative bias temperature instability lifetime prediction: problems and solutions. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2013

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