Author:
Caspi Eylon,Chu Michael,Huang Randy,Yeh Joseph,Wawrzynek John,DeHon André
Publisher
Springer Berlin Heidelberg
Reference18 articles.
1. Altera Corporation, 2610 Orchard Parkway, San Jose, CA 95134-2020. APEX Device Family, March 1999. http://www.altera.com/html/products/apex.html .
2. Gordon Brebner. TheSwappable Logic Unit:a Paradigm forVirtual Hardware. In Proceedings of the 5th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM’97), pages 77–86, April 1997.
3. ERL Technical Report 93/69;J. T. Buck,1993
4. David E. Culler, Seth C. Goldstein, Klaus E. Schauser, and Thorsten von Eicken. TAM — A Compiler Controlled Threaded Abstract Machine. Journal of Parallel and Distributed Computing, June 1993.
5. Jack B. Dennis. Data Flow Supercomputers. Computer, 13:48–56, November 1980.
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