On-line Testing for VLSI—A Compendium of Approaches-Reference-Cited by-同舟云学术

On-line Testing for VLSI—A Compendium of Approaches

Published:1998 Issue: Volume: Page:7-20
ISSN:0929-1296
Container-title:On-Line Testing for VLSI
language:
Short-container-title:

Author:

Nicolaidis M.,Zorian Y.

Publisher

Springer US

Link

http://link.springer.com/content/pdf/10.1007/978-1-4757-6069-9_1.pdf

Reference125 articles.

1. M. Nicolaidis, “New TAC—On-Line Testing,” IEEE Test Technology Newsletter, Aug. 1994.

2. W.C. Carter and P.R. Schneider, “Design of Dynamically Checked Computers,” Proc. 4th Congress IFIP, Edinburgh, Scotland, Aug. 5–10, 1968, Vol. 2, pp. 878–883.

3. D.A. Anderson, “Design of Self-Checking Digital Networks Using Coding Techniques Coordinates. Sciences Laboratory,” Report R/527, University of Illinois, Urbana, Sept. 1971.

4. J.E. Smith and G. Metze, “Strongly Fault Secure Logic Networks,” IEEE Trans. on Comp, Vol. C-27, No. 6, June 1978.

5. E.J. McCluskey and F.W. Clegg, “Fault Equivalence in Combinational Logic Networks,” IEEE Trans. Comp, Vol. C-20, pp. 1286–1293, Nov. 1971.

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