Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance

Author:

Moaiyeri Mohammad Hossein,Razi Farzad

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Modelling and Simulation,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference30 articles.

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3. Hisamoto, D., Lee, W.-C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., Anderson, E., King, T.-J., Bokor, J., Hu, C.: FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Devices 47(12), 2320–2325 (2000)

4. Choi, Y.-K., Lindert, N., Xuan, P., Tang, S., Ha, D., Anderson, E., King, T.-J., Bokor, J., Hu, C.: Sub-20 nm CMOS FinFET technologies. In: International Electron Devices Meeting, IEDM’01, pp. 19.1.1–10.1.4 (2001)

5. Hu, T.J., King, V., Subramanian, L., Chang, X., Huang, Y.K., Choi, J.T., Kedzierski, N., Lindert, J., Bokor, W., Lee, W.C.: FinFET transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture. U.S. Patent No. 6,413,802. 2 July (2002)

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