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Sub-10 nm Carbon Nanotube Transistor

Published:2012-01-18 Issue:2 Volume:12 Page:758-762
ISSN:1530-6984
Container-title:Nano Letters
language:en
Short-container-title:Nano Lett.

Author:

Franklin Aaron D.¹,Luisier Mathieu²,Han Shu-Jen¹,Tulevski George¹,Breslin Chris M.¹,Gignac Lynne¹,Lundstrom Mark S.³,Haensch Wilfried¹

Affiliation:

1. IBM T. J. Watson Research Center, Yorktown Heights, New York 10598, United States

2. Integrated Systems Laboratory, ETH Zurich, 8092 Zurich, Switzerland

3. School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907, United States

Publisher

American Chemical Society (ACS)

Subject

Mechanical Engineering,Condensed Matter Physics,General Materials Science,General Chemistry,Bioengineering

Link

https://pubs.acs.org/doi/pdf/10.1021/nl203701g

Reference22 articles.

1. Silicon Device Scaling to the Sub-10-nm Regime

2. Is Silicon's Reign Nearing Its End?

3. Intel 22nm 3-D Tri-Gate Transistor Technology.http://newsroom.intel.com/docs/DOC-2032, 2011.

4. Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications

5. In Search of “Forever,” Continued Transistor Scaling One New Material at a Time

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