A High Throughput In-MRAM-Computing Scheme Using Hybrid p-SOT-MTJ/GAA-CNTFET-Reference-Cited by-同舟云学术

A High Throughput In-MRAM-Computing Scheme Using Hybrid p-SOT-MTJ/GAA-CNTFET

Published:2024-02 Issue:2 Volume:71 Page:606-619
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Tong Zhongzhen¹^ORCID,Xu Yilin²,Liu Yunlong³,Duan Xinrui²,Tang Hao²,Zhao Suteng²,Li Chenghang²,Lin Zhiting³^ORCID,Wu Xiulong³^ORCID,Wang Zhaohao²^ORCID,Lin Xiaoyang¹^ORCID

Affiliation:

1. National Key Laboratory of Spintronics, Institute of International Innovation, Beihang University, Hangzhou, Yuhang, China

2. School of Integrated Circuit Science and Engineering, Beihang University, Beijing, China

3. School of Integrated Circuits, Anhui Provincial High-Performance Integrated Circuit Engineering Research Center, Anhui University, Hefei, China

Funder

Beijing Natural Science Foundation

National Natural Science Foundation of China

Young Elite Scientists Sponsorship Program by the China Association for Science and Technology

International Mobility Project

Fundamental Research Funds for Central Universities of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10416295/10367767.pdf?arnumber=10367767

Reference53 articles.

1. Celebrating 75 years of the transistor A look at the evolution of Moore’s Law innovation

2. Status and Future Prospects of CMOS Scaling and Moore's Law - A Personal Perspective

3. A Variation-Aware Ternary Spin-Hall Assisted STT-RAM Based on Hybrid MTJ/GAA-CNTFET Logic

4. A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

5. Exploiting Carbon Nanotube FET and Magnetic Tunneling Junction for Near-Memory-Computing Paradigm

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