Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure-Reference-Cited by-同舟云学术

Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

Published:2011-04-08 Issue:1-2 Volume:10 Page:222-228
ISSN:1569-8025
Container-title:Journal of Computational Electronics
language:en
Short-container-title:J Comput Electron

Author:

Rana Ashwani K.,Chand Narottam,Kapoor Vinod

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Modeling and Simulation,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Link

http://link.springer.com/content/pdf/10.1007/s10825-011-0357-8.pdf

Reference20 articles.

1. Choi, C.-H., Nam, K.Y., Yu, Z., Dutton, R.W.: Impact of gate direct tunneling current on circuit performance: a simulation study. IEEE Trans. Electron Devices 48, 2823–2829 (2001)

2. International Technology Roadmap for Semiconductors, http://public.itrs.net/Files/2001ITRS/Home.html

3. Taur, Y.: CMOS design near the limits of scaling. IBM J. Res. Develop. 46(2/3), 213–222 (2002)

4. Sirisantana, N., Wei, L., Roy, K.: High performance low-power CMOS circuits using multiple channel length and multiple oxide thickness. In: Proc. of IEEE ICCD, pp. 227–232 (2000)

5. Hamzaoglu, F., Stan, M.: Circuit-level techniques to control gate leakage for sub 100 nm CMOS. In: Proc. ISLPED, pp. 60–63 (2002)

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