A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops-Reference-Cited by-同舟云学术

A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops

Published:2017-01-03 Issue:9 Volume:36 Page:3514-3526
ISSN:0278-081X
Container-title:Circuits, Systems, and Signal Processing
language:en
Short-container-title:Circuits Syst Signal Process

Author:

Estebsari Motahhareh,Gholami Mohammad,Ghahramanpour Mohammad Javad

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Link

http://link.springer.com/article/10.1007/s00034-016-0481-6/fulltext.html

Reference15 articles.

1. C.C. Chung, C.L. Chang, A wide-range all-digital delay-locked loop in 65nm CMOS technology. In 2010 International Symposium on VLSI Design Automation and Test (VLSI-DAT), Apr 26. IEEE (2010), pp. 66–69

2. M. Estebsari, M. Gholami, M.J. Ghahramanpour, A wide frequency range delay line for fast-locking and low power delay-locked-loops. Analog Integrated Circuits and Signal Processing (2016), pp. 1–8

3. M. Gholami, A novel low power architecture for DLL-based frequency synthesizers. Circuits Syst. Signal Process. 32(2), 781–801 (2013)

4. M. Gholami, Total jitter of delay-locked loops due to four main jitter sources. IEEE Trans. Very Large Scale Integr. Syst. 24(6), 2040–2049 (2016)

5. M. Gholami, H. Rahimpour, G. Ardeshir, H. Miar-Naimi, A new fast-lock, low-jitter, and all-digital frequency synthesizer for DVB-T receivers. Int. J. Cir. Theory Appl. 43(5), 566–578 (2015)

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