An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division-Reference-Cited by-同舟云学术

An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division

Published:2017-04-17 Issue:1 Volume:37 Page:383-407
ISSN:0278-081X
Container-title:Circuits, Systems, and Signal Processing
language:en
Short-container-title:Circuits Syst Signal Process

Author:

Jaiswal Manish Kumar^ORCID,So Hayden K.-H.

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Link

http://link.springer.com/article/10.1007/s00034-017-0559-9/fulltext.html

Reference24 articles.

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2. D.H. Bailey, R. Barrio, J.M. Borwein, High-precision computation: mathematical physics and dynamics. Appl. Math. Comput. 218(20), 10106–10121 (2012). doi: 10.1016/j.amc.2012.03.087

3. S. Banescu, F. de Dinechin, B. Pasca, R. Tudoran, Multipliers for floating-point double precision and beyond on FPGAs. SIGARCH Comput. Archit. News 38, 73–79 (2011). doi: 10.1145/1926367.1926380

4. L. Dadda, Some schemes for parallel multipliers. Alta Freq. 34, 349–356 (1965)

5. M.M. Daniel, F.S. Diego, H.L. Carlos, A.R. Mauricio, Tradeoff of FPGA design of a floating-point library for arithmeitic operators. J. Integr. Circuits Syst. 5(1), 42–52 (2010)

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