Author:
Hanuman C. R. S.,Kamala J.,Aruna A. R.
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Information Systems,Theoretical Computer Science,Software
Reference29 articles.
1. IEEE Computer Society (2008) IEEE Standard for Floating-point Arithmetic. IEEE standard 754-2008, August 2008.
http://ieeexplore.ieee.org/servlet/opac?punumber=4610933
2. Pimentel JJ, Bohnenstiehl B, Bass BM (2017) Hybrid hardware/software floating-point implementations for optimized area and throughput tradeoffs. IEEE Trans Very Large Scale Integr Syst 25(1):100–113
3. Jaiswal MK, So HK-H (2017) Area-efficient architecture for dual-mode double precision floating point division. IEEE Trans Circuits Syst-I 64(2):386–398
4. Escalante LP, Parra-Michel R, Castillo J, Gandara O (2015) Fast bit accurate reciprocal square root. Microprocessors Microsyst 39:74–82
5. Joldes M, Marty O, Muller J-M, Popescu V (2016) Arithmetic algorithms for extended precision using floating point expansions. IEEE Trans Comput 65(4):1197–1211
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