Design of Ternary Logic Circuits Using GNRFET and RRAM
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-023-02445-9.pdf
Reference41 articles.
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2. E. Abbasian, M. Gholipour, F. Izadinasab, Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design. Int. J. Circuit Theory Appl. 49(11), 3630–3652 (2021). https://doi.org/10.1002/cta.3108
3. E. Abbasian, M. Nayeri, A high-speed low-energy one-trit ternary multiplier circuit design in CNTFET technology. ECS J. Solid State Sci. Technol. 12 (2) (2023). https://doi.org/10.1149/2162-8777/acb8d9
4. E. Abbasian, M. Orouji, S.T. Anvari, A. Asadi, E. Mahmoodi, An ultra-low power and energy-efficient ternary half-adder based on unary operators and two Ternary 3:1 Multiplexers in 32-nm GNRFET technology. Int. J. Circuit Theory Appl. (2023). https://doi.org/10.1002/cta.3667
5. E. Abbasian, S. Sofimowloodi, A high-performance and energy-efficient ternary multiplier using CNTFETs. Arab. J. Sci. Eng. (2023). https://doi.org/10.1007/s13369-023-07618-x
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