A Reduced-sp- $$\hbox {D3L}_{\mathrm{sum}}$$ D3L sum Adder-Based High Frequency $$4\times 4$$ 4 × 4 Bit Multiplier Using Dadda Algorithm-Reference-Cited by-同舟云学术

A Reduced-sp- $$\hbox {D3L}_{\mathrm{sum}}$$ D3L sum Adder-Based High Frequency $$4\times 4$$ 4 × 4 Bit Multiplier Using Dadda Algorithm

Published:2015-11-24 Issue:9 Volume:35 Page:3113-3134
ISSN:0278-081X
Container-title:Circuits, Systems, and Signal Processing
language:en
Short-container-title:Circuits Syst Signal Process

Author:

Shabbir Zain,Ghumman Anas Razzaq,Chaudhry Shabbir Majeed

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s00034-015-0201-7.pdf

Reference22 articles.

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2. S. Agwa, E. Yahya, Y. Ismail, Variability Mitigation Using Correction Function Technique. in Proceedings of 20th ICECS, (Dubai, UAE, 2013)

3. M. Aktan, V.G. Oklobdzija, D. Baran, Multiplier Structures for Low Power Applications in Deep-CMOS. in Proceedings of ISCAS’11, (Rio de Janeiro, Brazil, 2011), pp. 1061–1064

4. Y. Bansal, C. Madhu, P. Kaur, High Speed Vedic Multiplier Designs A Review. in Proceedings of RAECS 2014, (Chandigarh, India, 2014), pp. 1–6

5. C.H. Bennet, Logical reversibility of computation. IBM J. Res. Dev. 6, 525 (1973)

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