Study of Linearity Performance of Graded Channel Gate Stacks Double Gate MOSFET with Respect to High-K Oxide Thickness
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
http://link.springer.com/content/pdf/10.1007/s12633-019-00257-8.pdf
Reference27 articles.
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3. Taur Y, Liang X, Wang W, Lu H (2004) A continuous, analytic drain-current model for DG MOSFETs. IEEE Electron Device Letters 25(2):107–109
4. Balestra F, Cristoloveanu S, Benachir M, Brini J, Elewa T (1987) Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance. IEEE Electron Device Letters 8(9):410–412
5. Kranti A, Armstrong GA (2006) Optimization of the source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFETs with high-κ gate dielectrics. Semicond Sci Technol 21(12):1563–1572
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