Study of DC and Analog/RF Performances Analysis of Short Channel Surrounded Gate Junctionless Graded Channel Gate Stack MOSFET
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s42341-023-00455-7.pdf
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4. S. Gundapaneni, S. Ganguly, A. Kottantharayil, Enhanced Electrostatic integrity of short-channel junctionless transistor with high-$\kappa $ spacers. IEEE Electron Device Lett. 32(10), 1325–1327 (2011)
5. J.P. Colinge, A. Kranti, R. Yan, C.W. Lee, I. Ferain, R. Yu, N.D. Akhavan, P. Razavi, Junctionless nanowire transistor (JNT): properties and design guidelines. Solid-State Electron. 65, 33–37 (2011)
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