Geometrical Variability Impact on the Performance of Sub - 3 nm Gate-All-Around Stacked Nanosheet FET
Author:
Yadav NishaORCID, Jadav Sunil, Saini Gaurav
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Reference28 articles.
1. Yeap G, Lin SS, Chen YM, Shang HL, Wang PW, Lin HC, Peng YC, Sheu JY, Wang M, Chen X, Yang BR, Lin CP, Yang FC, Leung YK, Lin DW, Chen CP, Yu KF, Chen DH, Chang CY, Chen HK, Hung P, Hou CS, Cheng YK, Chang J, Yuan L, Lin CK, Chen CC, Yeo YC, Tsai MH, Lin HT, Chui CO, Huang KB, Chang W, Lin HJ, Chen KW, Chen R, Sun SH, Fu Q, Yang HT, Chiang HT, Yeh CC, Lee TL, Wang CH, Shue SL, Wu CW, Lu R, Lin WR, Wu J, Lai F, Wu YH, Tien BZ, Huang YC, Lu LC, He J, Ku Y, Lin J, Cao M, Chang TS, Jang SM (2019) 5nm CMOS production technology platform featuring full-fledged EUV, and high mobility channel FinFETs with densest 0.021 um2 SRAM cells for mobile SoC and high performance computing applications. IEEE Int Electron Devices Meeting (IEDM), Section 36.7. https://doi.org/10.1109/IEDM19573.2019.8993577 2. Yeung CW, Zhang J, Chao R, Kwon O, Vega R, Tsutsui G, Miao X, Zhang C, Sohn CW, Moon BK, Razavieh A, Frougier J, Greene A, Galatage R, Li J, Wang M, Loubet N, Robison R, Basker V, Yamashita T, Guo D (2018) Channel geometry impact and narrow sheet effect of stacked nanosheet. IEEE Int Electron Devices Meeting (IEDM):28.6.1–28.6.4. https://doi.org/10.1109/IEDM.2018.8614608 3. Loubet N, Hook T, Montanini P, Yeung CW, Kanakasabapathy S, Guillom M, Yamashita T, Zhang J, Miao X, Wang J, Young A, Chao R, Kang M, Liu Z, Fan S, Hamieh B, Sieg S, Mignot Y, Xu W, Seo SC, Yoo J, Mochizuki S, Sankarapandian M, Kwon O, Carr A, Greene A, Park Y, Frougier J, Galatage R, Bao R, Shearer J, Conti R, Song H, Lee D, Kong D, Xu Y, Arceo A, Bi Z, Xu P, Muthinti R, Li J, Wong R, Brown D, Oldiges P, Robison R, Arnold J, Felix N, Skordas S, Gaudiello J, Standaert T, Jagannathan H, Corliss D, Na MH, Knorr A, Wu T, Gupta D, Lian S, Divakaruni R, Gow T, Labelle C, Lee S, Paruchuri V, Bu H, Khare M (2017) Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. Proc IEEE Symp VLSI Technol:230–231. https://doi.org/10.23919/VLSIT.2017.7998183 4. Yakimets D, Bardon MG, Jang D, Schuddinck P, Sherazi Y, Weckx P, Miyaguchi K, Parvais B, Raghavan P, Spessot A, Verkest D, Mocuta A (2017) Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology. IEEE Int Electron Devices Meeting (IEDM):20.4.1–20.4.4. https://doi.org/10.1109/IEDM.2017.8268429 5. Nagy D, Espineira G, Indalecio G, Loureiro AJ, Kalna K, Seoane N (2020) Benchmarking of FinFET, nanosheet, and nanowire FET architectures for future technology nodes. IEEE Access 8:53196–53202. https://doi.org/10.1109/ACCESS.2020.2980925
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
|
|