Performance Comparison Between Inversion Mode and Junctionless Cylindrical Gate All Around Si Nanowire MOSFET Using Dual Metal Gate Work Function Engineering for Upcoming Sub 5 nm Technology Node
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-023-02730-x.pdf
Reference50 articles.
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2. Baidya A, Baishya S, Lenk TR (2017) Impact of thin high-κ dielectrics and gate metals on RF characteristics of 3D double gate junctionless transistor. Mater Sci Semicond Process 71:413–420
3. Lema FA, Wang X, Amoroso SM, Riddet C, Cheng B, Shifren L, Aitken R, Sinha S, Yeric G, Asenov A (2014) Performance and Variability of Doped Multithreshold FinFETs for 10-nm CMOS. IEEE Trans Electron Devices 61:3372–3378
4. Das UK, Bardon MG, Jang D, Eneman G, Schuddinck P, Yakimets D, Raghavan P, Groeseneken G (2017) Limitations on Lateral Nanowire Scaling Beyond 7nm Node. IEEE Electron Device Lett 38:9–11
5. Suddapalli SR, Nistala BR (2021) The analog/RF performance of a strained-Si graded-channel dual-material double-gate MOSFET with interface charges. J Comput Electron 20:492–502
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