1. Thompson, S.E., Armstrong, M., Auth, C., Cea, S., Chau, R., Glass, G., Hoffman, T., Klaus, J., Ma, Z., Mcintyre, B., Murthy, A., Obradovic, B., Shifren, L., Sivakumar, S., Tyagi, S., Ghani, T., Mistry, K., Bohr, M., El-Mansy, Y.: A logic nanotechnology featuring strained-silicon. IEEE Electron Device Lett. 25(4), 191–193 (2004)
2. Jurczak, M., Skotnicki, T., Ricci, G., Campidelli, Y., Hernandez, C., Bensahel, D.: Study on enhanced performance in NMOSFETs on strained silicon. In: 29th European Solid-State Device Research Conference, vol. 1, pp. 304–307 (1999)
3. Sanuki, T., Oishi, A., Morimasa, Y., Aota, S., Kinoshita, T., Hasumi, R., Takegawa, Y., Isobe, K., Yoshimura, H., Iwai, M., Sunouchi, K., Noguchi, T.: Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology. In: IEEE International Electron Devices Meeting 2003, pp. 3.5.1–3.5.4 (2003)
4. Keith, S., Bufler, F.M., Meinerzhagen, B.: Full band Monte-Carlo device simulation of an 0.1 um N-channel MOSFET in strained silicon material. In: 27th European Solid-State Device Research Conference, pp. 200–203 (1997)
5. Nguyen, C., Pham, A., Jungemann, C., Meinerzhagen, B.: Study of charge carrier quantization in strained Si-nMOSFETs. Mater. Sci. Semicond. Process. 8(1), 363–366 (2005)