Gate Oxide Variability Analysis of a Novel 3 nm Truncated Fin–FinFET for High Circuitry Performance
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-020-00734-5.pdf
Reference25 articles.
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3. Kumar A, Tripathi MM, Chaujar R (2018) Reliability issues of In2O5Sn gate electrode Recessed Channel MOSFET: impact of Interface trap charges and temperature. IEEE Trans Electron Devices 65(3):860–866. https://doi.org/10.1109/TED.2018.2793853
4. Kranti A, Armstrong GA (2007) Design and optimization of FinFETs for ultra-low-voltage analog applications. IEEE Trans Electron Devices 54(12):3308–3316. https://doi.org/10.1109/TED.2007.908596
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