Analog/RF Performance and Effect of Temperature on Ferroelectric Layer Improved FET device with Spacer
Author:
Funder
Council of Scientific and Industrial Research, India
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-022-01822-4.pdf
Reference42 articles.
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2. Kumar B., Chaujar R. (2021) Analog and rf performance evaluation of junctionless accumulation mode (jam) gate stack gate all around (gs-gaa) finfet. Silicon 13(3):919–927
3. Waldrop M. M. (2016) More than moore. Nature 530(7589):144–148
4. Pathak Y., Malhotra B.D., Chaujar R. (2021) Tcad analysis and simulation of double metal negative capacitance fet (dm ncfet). In: 2021 Devices for Integrated Circuit (DevIC), pp. 224–228, IEEE
5. Lee M., Chen P.-G., Liu C., Chu K., Cheng C.-C., Xie M.-J., Liu S.-N., Lee J.-W., Huang S.-J., Liao M.-H., et al. (2015) Prospects for ferroelectric hfzrox fets with experimentally cet= 0.98 nm, ssfor= 42mvdec, ssrev= 28mvdec, switch-off-lt
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