Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-021-01471-z.pdf
Reference31 articles.
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2. Barraud S, et al. (2017) Performance and design considerations for gate-all-around stacked-NanoWires FETs, 2017 IEEE International Electron Devices Meeting (IEDM), p. 29.2.1–29.2.4. https://doi.org/10.1109/IEDM.2017.8268473
3. Yakimets D, Eneman G, Schuddinck P, Huynh Bao T, Garcia Bardon M, Raghavan P, Veloso A, Collaert N, Mercha A, Verkest D, Thean AV-Y, De Meyer K (May 2015) Vertical GAAFETs for the ultimate CMOS scaling. IEEE Trans Electron Devices 62(5):1433–1439. https://doi.org/10.1109/TED.2015.2414924
4. Wei Lu and Charles M Lieber (2006) Semiconductor nanowires J Phys D Appl Phys 39:R387. Available: http://stacks.iop.org/0022-3727/39/i=21/a=R01
5. Kola SR, Li Y, Thoti N (2020) Random telegraph noise in gate-all-around silicon nanowire MOSFETs induced by a single charge trap or random interface traps. J Comput Electron 19:253–262. https://doi.org/10.1007/s10825-019-01438-9
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