Junction-less SOI FET with an Embedded p+ Layer: Investigation of DC, RF, and Negative Capacitance Characteristics
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-023-02315-8.pdf
Reference42 articles.
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2. Jazaeri F, Barbut L, Sallese J (2013) Modeling and design space of junctionless symmetric DG MOSFETs with long channel. IEEE Trans Electron Devices 60(7):2120–2127. https://doi.org/10.1109/TED.2013.2261073
3. Motamedi A, Orouji AA, Madadi D (2022) Physical analysis of β-Ga2O3 gate-all-around nanowire junctionless transistors: short-channel effects and temperature dependence. J Comput Electron 21(1):197–205. https://doi.org/10.1007/s10825-021-01837-x
4. Bolokian M, Orouji AA, Abbasi A, Madadi D (2022) Realizing of double-gate junctionless FET depletion region for 6 nm regime with an efficient layer. Phys Status Solidi. https://doi.org/10.1002/pssa.202200214
5. Madadi D, Orouji AA (2022) Stacked single gate SOI 4H-SiC junctionless FET with a buried P-type 4H-SiC layer. Phys Status Solidi. https://doi.org/10.1002/pssa.202100504
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