Parametric Investigation and Design of Junctionless Nanowire Tunnel Field Effect Transistor-Reference-Cited by-同舟云学术

Parametric Investigation and Design of Junctionless Nanowire Tunnel Field Effect Transistor

Published:2021-09-20 Issue: Volume: Page:
ISSN:1876-990X
Container-title:Silicon
language:en
Short-container-title:Silicon

Author:

Kumar Parveen^ORCID,Raj Balwinder

Publisher

Springer Science and Business Media LLC

Subject

Electronic, Optical and Magnetic Materials

Link

https://link.springer.com/content/pdf/10.1007/s12633-021-01371-2.pdf

Reference36 articles.

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3. Sharma S, Raj B, Khosla M (2016) Comparative analysis of MOSFET CNTFET and NWFET for high performance VLSI circuit design. A Rev J VLSI Des Tools Technol 6:19–32

4. Duvvury C (1986) A guide to short-channel effects in MOSFETs. IEEE Circuits Devices Mag 2:6–10

5. Roy K, Mukhopadhyay S, Mahmoodi-Meimand H (2003) Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc IEEE 91:305–327

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