Optimal VLSI Delay Tuning by Wire Shielding
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Management Science and Operations Research,Control and Optimization
Link
http://link.springer.com/content/pdf/10.1007/s10957-016-0960-8.pdf
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3. Alioto, M., Palumbo, G., Pennisi, M.: Understanding the effect of process variations on the delay of static and domino logic. IEEE Trans. VLSI Syst. 18(5), 697–710 (2010)
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5. Rubinstein, J., Penfield, P.J., Horowitz, M.: Signal delay in RC tree networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(3), 202–211 (1983)
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