1. Semiconductor Industry Association. 2011 International Technology Roadmap for Semiconductors [M]. Berlin: Springer-Verlag, 2011.
2. Sahoo S, Datta M, Kar R. An efficient dynamic power estimation method for on-chip VLSI interconnects [C]// International Conference on Emerging Applications of Information Technology. Piscataway: IEEE, 2011: 379–382.
3. Moiseev K, Wimer S, Kolodny A. Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing [J]. Integration the VLSI Journal, 2015, 48(1): 116–128.
4. Frankel B, Wimer S. Optimal VLSI delay tuning by wire shielding [J]. Journal of Optimization Theory and Applications, 2016, 170(3): 1060–1067.
5. Kar R, Maheshwari V, Mondal S, et al. Bhattacharjee. A novel power estimation method for on-chip VLSI distributed RLCG global interconnects using model order reduction technique [C]// International Conference on Advances in Computer Engineering. Piscataway: IEEE, 2010: 105–109.