Author:
Agarwal A.,Blaauw D.,Zolotov V.
Cited by
66 articles.
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1. Agile Full-Chip Sign-Off in the Post-Moore Era;2023 China Semiconductor Technology International Conference (CSTIC);2023-06-26
2. A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-04
3. 2D physically unclonable functions of the arbiter type;Informatics;2023-03-29
4. Fault-Tolerant Circuits;Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design;2023
5. Joint Timing Yield and Lifetime Reliability Optimization of Integrated Circuits;Lifetime Reliability-aware Design of Integrated Circuits;2022-11-17