High Level Test Economics Advisor (Hi-TEA)-Reference-Cited by-同舟云学术

High Level Test Economics Advisor (Hi-TEA)

Published:1994 Issue:2-3 Volume:5 Page:195-206
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Abadir Magdy,Parikh Ashish,Bal Linda,Sandborn Peter,Murphy Cynthia

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/BF00972079.pdf

Reference4 articles.

1. Economics of Design and Test for Electronic Circuits and Systems, A.P. Ambler, M. Abadir, and S. Sastry, (eds.), Ellis Horwood Publisher, 1992, contains extended versions of papers presented at the First International Workshop on the Economics of Design and Test, Austin, Texas.

2. T.W. Williams and N.C. Brown, ?Defect Level as a Function of Fault Coverage?,IEEE Trans. on Computers, vol. C030, pp. 987?988, Dec. 1981.

3. C. Dislis, J. Dick, and A. P. Ambler, ?An Economics Based Test Strategy Planner for VLSI Design?,Proceedings of the 2nd European Test Conference, 1991.

4. C. Dislis, A.P. Ambler, and J. Dick, ?Economic Effects in Design and Test?,IEEE Design and Test of Computers, vol. 6, Dec. 1991.

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3. IC manufacturing test cost estimation at early stages of the design cycle;Microelectronics Journal;1999-08

4. Economics modeling of multichip modules testing strategies;IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B;1998-11

5. Modeling testing-strategies for yield enhancement of multichip module systems;IEEE Transactions on Reliability;1997-06