Design of High Speed Vedic Multiplier for Decimal Number System-Reference-Cited by-同舟云学术

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Design of High Speed Vedic Multiplier for Decimal Number System

Published:2012 Issue: Volume: Page:79-88
ISSN:0302-9743
Container-title:Progress in VLSI Design and Test
language:
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Author:

Saha Prabir,Banerjee Arindam,Dandapat Anup,Bhattacharyya Partha

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-31494-0_10.pdf

Reference18 articles.

1. James, R.K., Shahana, T.K., Jacob, K.P., Sasi, S.: Decimal Multiplication using compact BCD Multiplier. In: Proc. IEEE Int. Conf. on Electronics Design (ICED 2008), Penang, pp. 1–6 (2008)

2. James, R.K., Jacob, K.P., Sasi, S.: Performance analysis of double digit decimal multiplier on various FPGA logic families. In: Proc. IEEE Int. Conf. on Programmable Logic, Sao Carlos, pp. 165–170 (2009)

3. Sutter, G., Todorovich, E., Bioul, G., Vazquez, M., Deschamps, J.P.: FPGA Implementations of BCD Multipliers. In: Proc. IEEE Int. Conf. on Reconfigurable Computing and FPGAs (ReConFig 2009), Quintana Roo, pp. 36–41 (2009)

4. Véstias, M.P., Neto, H.C.: Parallel decimal multipliers using binary multipliers. In: Proc. IEEE VI Southern Programmable Logic Conference (SPL), Ipojuca, pp. 73–78 (2010)

5. Jaberipur, G., Kaivani, A.: Binary-coded decimal digit multipliers. IET Journal on Computer & Digital Techniques, 377–381 (2007)

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