HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs

Author:

Morales-Villanueva Aurelio,Gordon-Ross Ann

Publisher

Springer Berlin Heidelberg

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices;Electronics;2022-12-27

2. A Survey: FPGA‐Based Dynamic Scheduling of Hardware Tasks;Chinese Journal of Electronics;2021-11

3. Scheduling Algorithms for Reconfigurable Systems;Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms;2021

4. A novel BRAM content accessing and processing method based on FPGA configuration bitstream;Microprocessors and Microsystems;2017-03

5. Migration of long-running Tasks between Reconfigurable Resources using Virtualization;ACM SIGARCH Computer Architecture News;2017-01-11

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