Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration-Reference-Cited by-同舟云学术

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Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration

Published:2009-11 Issue:11 Volume:17 Page:1650-1654
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Corbetta S.,Morandi M.,Novati M.,Santambrogio M.D.,Sciuto D.,Spoletini P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/5290268/04801552.pdf?arnumber=4801552

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization;Proceedings of the 50th Annual International Symposium on Computer Architecture;2023-06-17

2. A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip;Journal of Parallel and Distributed Computing;2018-02

3. A General Low-Cost Fast Hybrid Reconfiguration Architecture for FPGA-Based Self-Adaptive System;IEICE Transactions on Information and Systems;2018

4. Efficient totally-ordered subset generation, with application in partial reconfiguration;2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2017-05

5. Relocating Encrypted Partial Bitstreams by Advance Task Address Loading;2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2017-04

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