Token3D: Reducing Temperature in 3D Die-Stacked CMPs through Cycle-Level Power Control Mechanisms-Reference-Cited by-同舟云学术

Token3D: Reducing Temperature in 3D Die-Stacked CMPs through Cycle-Level Power Control Mechanisms

Published:2011 Issue: Volume: Page:295-309
ISSN:0302-9743
Container-title:Euro-Par 2011 Parallel Processing
language:
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Author:

Cebrián Juan M.,Aragón Juan L.,Kaxiras Stefanos

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-23400-2_28

Reference24 articles.

1. Ajami, A.H., Banerjee, K., Pedram, M.: Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Trans. on CAD 24(6), 849–861 (2005)

2. Black, B., Annavaram, M., Brekelbaum, N., DeVale, J., Jiang, L., Loh, G.H., McCaule, D., Morrow, P., Nelson, D.W., Pantuso, D., Reed, P., Rupley, J., Shankar, S., Shen, J., Webb, C.: Die Stacking (3D) Microarchitecture. In: Proc. of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 469–479 (December 2006)

3. Brooks, D., Martonosi, M.: Dynamic thermal management for high-performance microprocessors. In: Proc. of the 7th Int. Symposium on High Performance Computer Architecture, HPCA (2001)

4. Cebrián, J.M., Aragón, J.L., García, J.M., Petoumenos, P., Kaxiras, S.: Efficient Microarchitecture Policies for Accurately Adapting to Power Constraints. In: Proc. of the 23rd Int. Parallel and Distributed Processing Symposium, IPDPS (2009)

5. Cebrián, J.M., Aragón, J.L., Kaxiras, S.: Power Token Balancing: Adapting CMPs to Power Constraints for Parallel Multithreaded Workloads. To appear in Proc. of the 25rd Int. Parallel and Distributed Processing Symposium (May 2011)

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