Author:
S. Rajendra Prasad,Madhavi B. K.,Kishore K. Lal
Publisher
Springer Berlin Heidelberg
Reference13 articles.
1. International Technology Roadmap for Semiconductors by Semiconductor Industry Association (2009), http://public.itrs.net
2. Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S., Yamada, J.: 1-V power supply high-speed digital circuit technology with multi threshold-voltage CMOS. IEEE J. Solid-State Circuits 30(8), 847–854 (1995)
3. Powell, M., Yang, S.H., Falsafi, B., Roy, K., Vijaykumar, T.N.: Gated-VDD: A Circuit Technique to Reduce Leakage in Deep-submicron Cache Memories. In: International Symposium on Low Power Electronics and Design, pp. 90–95 (2000)
4. Kim, K.K., Nan, H., Choi, K.: Power Gating for Ultra-Low Voltage Nanometer ICs. In: IEEE ISCAS (2010)
5. Patil, N., Lin, A., Zhang, J., Wong, H.S.P., Mitra, S.: Digital VLSI logic technology using Carbon Nanotube FETs: Frequently Asked Questions. In: 46th ACM-IEEE Design Automation Conference, pp. 304–309 (2009)
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献