Novel Power Gated (PG) and Sleep Body Bias (SBB) 6T CNTFET-Based SRAM Design for Ultra-Low-Power Application-Reference-Cited by-同舟云学术

Novel Power Gated (PG) and Sleep Body Bias (SBB) 6T CNTFET-Based SRAM Design for Ultra-Low-Power Application

Published:2022-09-04 Issue: Volume: Page:767-782
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
language:
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Author:

Kumar Hemant,Singh Balwinder,Srivastava Subodh,Siddiqui Gulman,Yadav Shekhar

Publisher

Springer Nature Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-19-0312-0_76

Reference25 articles.

1. Moaiyeri MH, Rahi A, Sharifi F, Navi K (2017) Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits. J Appl Res Technol 15:233–241. https://doi.org/10.1016/J.JART.2016.12.006

2. Gupta D (2020) Low-voltage analog integrated circuit design. In: Dhiman R, Chandel R (eds) Nanoscale VLSI. Energy systems in electrical engineering. Springer, Singapore. https://doi.org/10.1007/978-981-15-7937-0_1

3. Kim Y-B (2010) Challenges for nanoscale MOSFETs and emerging nanoelectronics. Trans Electr Electron Mater 11(3):93–105. https://doi.org/10.4313/TEEM.2010.11.3.093

4. Singh A, Khosla M, Raj B (2016) Comparative analysis of carbon nanotube field effect transistor and nanowire transistor for low power circuit design. J Nanoelectron Optoelectron 11(3):388–393. https://doi.org/10.1166/jno.2016.1913

5. Saha P, Jain A, Sarkar SK (2013) A comparative study of CMOS and carbon nanotube field effect transistor based inverter at 32 nm technology node., Asian J Chem 25:424–426

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