Author:
Šimková Marcela,Lengál Ondřej
Publisher
Springer Berlin Heidelberg
Reference11 articles.
1. Šimková, M., Lengál, O.: Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures. Technical Report FIT-TR-2012-03, FIT BUT (2012),
http://www.fit.vutbr.cz/~ilengal/pub/FIT-TR-2012-03.pdf
2. Lecture Notes in Computer Science;M. Šimková,2012
3. Lecture Notes in Computer Science;A. Adir,2011
4. Henftling, R., Zinn, A., Bauer, M., Zambaldi, M., Ecker, W.: Re-Use-Centric Architecture for a Fully Accelerated Testbench Environment. In: Proc. of DAC 2003, pp. 372–375. ACM (2003)
5. Kakoee, M.R., Riazati, M., Mohammadi, S.: Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. In: Proc. of DSD 2008, pp. 714–720. IEEE (2008)
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. FPGA Prototyping and Accelerated Verification of ASIPs;2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems;2015-04