Author:
Jiang Yunlian,Tian Kai,Shen Xipeng
Publisher
Springer Berlin Heidelberg
Reference36 articles.
1. Browne, S., Deane, C., Ho, G., Mucci, P.: PAPI: A portable interface to hardware performance counters. In: Proceedings of Department of Defense HPCMP Users Group Conference (1999)
2. Bulpin, J.R., Pratt, I.A.: Hyper-threading aware process scheduling heuristics. In: 2005 USENIX Annual Technical Conference, pp. 103–106 (2005)
3. Chandra, D., Guo, F., Kim, S., Solihin, Y.: Predicting inter-thread cache contention on a chip multi-processor architecture. In: Proceedings of the International Symposium on High Performance Computer Architecture (HPCA), pp. 340–351 (2005)
4. DeVuyst, M., Kumar, R., Tullsen, D.M.: Exploiting unbalanced thread scheduling for energy and performance on a cmp of smt processors. In: Proceedings of International Parallel and Distribute Processing Symposium, IPDPS (2006)
5. Ding, C., Zhong, Y.: Predicting whole-program locality with reuse distance analysis. In: Proceedings of ACM SIGPLAN Conference on Programming Language Design and Implementation, San Diego, CA, June 2003, pp. 245–257 (2003)
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