Author:
Akturk Ismail,Ozturk Ozcan
Publisher
Springer Science and Business Media LLC
Subject
Information Systems,Theoretical Computer Science,Software
Reference31 articles.
1. Moore, G.E.: Cramming more components onto integrated circuits. Proc. IEEE 86(1), 82–85 (1998).
https://doi.org/10.1109/JPROC.1998.658762
2. Olukotun, K., Nayfeh, B.A., Hammond, L., Wilson, K., Chang, K.: The case for a single-chip multiprocessor. In: Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems. ACM, New York, NY, USA, pp. 2–11 (1996).
https://doi.org/10.1145/237090.237140
3. Tullsen, D.M., Eggers, S.J., Levy, H.M.: Simultaneous multithreading: maximizing on-chip parallelism. In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, pp. 392–403. ACM, New York, NY, USA (1995).
https://doi.org/10.1145/223982.224449
4. Kumar, R., Tullsen, D.M.: Compiling for instruction cache performance on a multithreaded architecture. In: Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture, pp. 419–429. IEEE Computer Society Press, Los Alamitos, CA, USA (2002)
5. Zhang, E.Z., Jiang, Y., Shen, X.: Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs? In: Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 203–212. ACM, New York, NY, USA (2010).
https://doi.org/10.1145/1693453.1693482
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. SLITS: Sparsity-Lightened Intelligent Thread Scheduling;ACM SIGMETRICS Performance Evaluation Review;2023-06-26
2. SLITS: Sparsity-Lightened Intelligent Thread Scheduling;Abstract Proceedings of the 2023 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems;2023-06-19
3. Efficient thread‐to‐core mapping alternatives for application‐level redundant multithreading;Concurrency and Computation: Practice and Experience;2023-01-18
4. Mitigating execution unit contention in parallel applications using instruction‐aware mapping;Concurrency and Computation: Practice and Experience;2021-12-30