An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs-Reference-Cited by-同舟云学术

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An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs

Published:2011 Issue: Volume: Page:84-93
ISSN:0302-9743
Container-title:Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
language:
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Author:

Lazzari Cristiano,Fernandes Jorge,Flores Paulo,Monteiro José

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-17752-1_9

Reference11 articles.

1. Gupta, A.K., Dally, W.J.: Topology optimization of interconnection networks. IEEE Comput. Archit. Lett. 5(1), 3 (2006)

2. Banerjee, K., Souri, S.J., Kapur, P., Saraswat, K.C.: 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proceedings of the IEEE 89(5), 602–633 (2001)

3. Li, F., Lin, Y., He, L., Chen, D., Cong, J.: Power modeling and characteristics of field programmable gate arrays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(11), 1712–1724 (2005)

4. Singh, A., Marek-Sadowska, M.: Efficient circuit clustering for area and power reduction in FPGAs. In: Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-Programmable Gate Arrays, FPGA 2002, pp. 59–66. ACM, New York (2002)

5. da Silva, R., Lazzari, C., Boudinov, H., Carro, L.: CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs. Microelectronics Journal 40(10), 1466–1470 (2009)

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3. Beyond Bits: A Quaternary FPGA Architecture Using Multi-Vt Multi-Vdd FDSOI Devices;2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL);2018-05

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