Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Computer Science Applications
Link
http://link.springer.com/article/10.1007/s11277-017-4226-z/fulltext.html
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3. Kim, N., Flautner, K., Blaauw, D., & Mudge, T. (2004). Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(2), 167–184.
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