An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box

Author:

Priya Sridevi Sathya,Karthigaikumar Palanivel,Siva Mangai N. M.,Kirti Gaurav Das P.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Reference33 articles.

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2. Farashahi, R. R., Rashidi, B., & Sayedi, S. M. (2014). FPGA based fast and high-throughput 2-slow returning 128-bit AES encryption algorithm. Microelectronic Journal, 45, 1014–1025.

3. Good, T., & Benaissa, M. (2007). Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment). IET Information Security, 1(1), 1–10.

4. Sireesha, K., & Madhava Rao, S. (2013). A novel approach of area optimized and pipelined FPGA implementation of AES encryption and decryption. International Journal of Scientific Research, 3(9), 1–5.

5. Gielata, A., Russek, P., & Wiatr, K. (2008). AES hardware implementation in FPGA for algorithm acceleration purpose. In Proceedings of the international conference on signals and electronic systems (ICSES) (pp. 137–140), September 14–17, 2008.

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