Author:
Farashahi Reza Rezaeian,Rashidi Bahram,Sayedi Sayed Masoud
Reference52 articles.
1. High-speed VLSI architectures for the AES algorithm;Zhang;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2004
2. Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment);Good;IET Inf. Secur.,2007
3. Cell array reconfigurable architecture for high-efficiency AES system;Hongge Li;Microelectron. Reliab.,2012
4. A new methodology to implement the AES algorithm using partial and dynamic reconfiguration;Granado-Criado;Integr., VLSI J.,2010
5. Kimmo U. Jarvinen, Matti T. Tommiska, Jorma O. Skytta, A Fully Pipelined Memoryless 17.8Gbps AES-128 Encryptor, in: Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA 2003), Monterey, CA, USA, February 2003, pp. 207–215.
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