Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization

Author:

Tomar Geetam Singh,George Marcus Lloyde

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Reference19 articles.

1. Perry, D. (1998). VHDL (3rd ed.). New York: McGraw-Hill.

2. Hennessey, J., & Patterson, D. (2003). Computer architecture. A quantitative approach (3rd ed.). San Francisco: Morgan Kaufmann Publishers.

3. Michael, D. C., Zhang, Y. Q., & Li, Q. (2005). Advanced digital with the verilog HDL etc translating. Beijing: Publishing House of Electronics Industry.

4. Kodali, R. K., Boppana, L., Yenamachintala, S. S. (2015). FPGA implementation of vedic floating point multiplier. In: IEEE international conference on signal processing, informatics, communication and energy systems (SPICES) (pp. 1–4). https://doi.org/10.1109/SPICES.2015.7091534 .

5. Abraham, S., Kaur, S., & Singh, S. (2015). Study of various high speed multipliers. In international conference on computer communication and informatics (ICCCI) (pp. 1–5). https://doi.org/10.1109/ICCCI.2015.7218139 .

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