Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures

Author:

Beechu Naresh Kumar ReddyORCID,Moodabettu Harishchandra Vasantha,Yernad Balachandra Nithin Kumar

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Reference22 articles.

1. Benini, Luca, & Micheli, G. D. (2002). Networks on chips: A new SoC paradigm. IEEE Computer, 35(1), 70–78.

2. Bertozzi, D., & Benini, L. (2004). Xpipes: A network-on-chip architecture for gigascale system on chip. IEEE Circuits and Systems, 4(2), 18–31.

3. Beechu, N. K. R., et al. (2017). High-performance and energy-efficient fault-tolerance core mapping in NoC. Sustainable Computing, Informatics and Systems. https://doi.org/10.1016/j.suscom.2017.08.004 .

4. Murali, S., & De Micheli, G. (2004) Bandwidth-constrained mapping of cores onto NoC architectures. In: Proceedings design automation and test in Europe conference and exhibition.

5. Chou, C.-L., & Marculescu, R. (2008) Contention-aware application mapping for network-on-chip communication architectures. IEEE international conference on computer design (pp. 164–169).

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