High-performance and energy-efficient fault-tolerance core mapping in NoC

Author:

Beechu Naresh Kumar Reddy,Moodabettu Harishchandra Vasantha,Yernad Balachandra Nithin Kumar

Funder

Department of Electronics and Information Technology, Ministry of Communication & IT, Government of India

Media Lab Asia

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science

Reference25 articles.

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4. Xpipes. A network-on-chip architecture for gigascale system on chip;Bertozzi;IEEE Circ. Syst.,2004

5. Energy and performance evaluation of a dimension order routing algorithm for mesh of tree based network-on-chip architecture;Manna,2010

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