Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Computer Science Applications
Link
https://link.springer.com/content/pdf/10.1007/s11277-022-10084-7.pdf
Reference33 articles.
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3. Gear, K. W., Sánchez-Macián, A., & Maestro, J. A. (2022). An analysis of FPGA configuration memory SEU accumulation and a preventative scrubbing technique. Microprocessors and Microsystems, 90, 104467.
4. Gavaskar, K., & Ragupathy, U. S. (2019). Low power self-controllable voltage level and low swing logic based 11T SRAM cell for high speed CMOS circuits. Analog Integrated Circuits and Signal Processing, 100(1), 61–77.
5. Prasad, G., Mandi, B. C., & Ali, M. (2021). Low power and write-enhancement RHBD 12T SRAM cell for aerospace applications. Analog Integrated Circuits and Signal Processing, 107(2), 377–388.
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