Introduction-Reference-Cited by-同舟云学术

Introduction

Published:1996 Issue: Volume: Page:1-18
ISSN:
Container-title:Low Power Design Methodologies
language:
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Author:

Rabaey Jan M.,Pedram Massoud,Landman Paul E.

Publisher

Springer US

Link

http://link.springer.com/content/pdf/10.1007/978-1-4615-2307-9_1

Reference30 articles.

1. M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou. “ Precomputation-based Sequential Logic Optimization for Low Power. ” InProceedings of the 1994 International Workshop on Low Power Designpages 57–62, April 1994.

2. H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, Menlo Park, CA, 1990.

3. L. Benini, M. Favalli, and B. Ricco, “Analysis of Hazard Contributions to Power Dissipation in CMOS IC’s,” 1994 International Workshop on Low-Power Design, Napa Valley, CA, pp. 27–32, April 1994.

4. W Bowhill, et al., “A 300 MHz Quad-Issue CMOS RISC Microprocessor,”Technical Digest of the 1995 ISSCC ConferenceSan Fransisco, 1995.

5. R. W. Brodersen et al, “Technologies for Personal Communications,” Proceedings of the VLSI Symposium ‘81 Conference, Japan, pp. 5–9, 1991.

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