Author:
Onabajo Marvin,Silva-Martinez Jose
Reference61 articles.
1. C. Chiang, J. Kawa, Design for Manufacturability and Yield for Nano-scale CMOS (Springer, Dordrecht, 2007), pp. 14–15
2. W. Zhao, Y. Cao, F. Liu, K. Agarwal, D. Acharyya, S. Nassif, K. Nowka, Rigorous extraction of process variations for 65 nm CMOS design, in Proceedings of European Solid-State Device Research Conference (ESSDERC), Sept 2007, pp. 89–92
3. G.W. Roberts, B. Dufort, Making complex mixed-signal telecommunication integrated circuits testable. IEEE Commun. Mag. 90–96 (1999)
4. A. Zjajo, J.P. de Gyvez, Evaluation of signature-based testing of RF/analog circuits. Proc. Eur.Test Symp. 62–67 (2005)
5. G.G.E. Gielen, Design methodologies and tools for circuit design in CMOS nanometer technologies, in Proceedings of European Solid-State Device Research Conference (ESSDERC), Sept 2006, pp. 21–32
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